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| ASTRA
Low Power Digital Spread Spectrum Transceiver
ASTRA Block Diagram (click for larger image) The SC2001 ASTRA is a low-cost, low power (3.3 V) digital Direct Sequence Spread Spectrum IC. It is a true Spread Spectrum/CDMA ASSP (Application Specific Standard Product) by its high degree of flexibility and programmability. The transmitter allows 2 channel QPSK/CDMA or 4 channel BPSK/CDMA transmission. The SC2001 ASTRA is a digital direct sequence spread spectrum chip, containing a programmable transmitter, receiver and auxiliary functions on-chip. The SC2001 ASTRA is part of a chip set. The second chip is either a DSP, such as the TMS320LC31, or a dedicated PSK demodulation chip. The SC2001 ASTRA interfaces to the DSP as a memory device, through a double-buffered on-chip interface. The data bus is 32 bits wide; the address bus is 32 bits. The SC2001 ASTRA contains the high-throughput digital functions which can be parameterized to be used in a broad class of transceivers. On the DSP, the final demodulation steps and (de)formatting, error correction and voice processing functions are executed; these functions are much more application-specific, hence full programmability is provided. The SC2001 ASTRA can operate both in CDMA (Code Division Multiple Access) and non-CDMA mode. In default CDMA mode, transmitter and receiver are able to demodulate 4 channel CDMA/BPSK or 2 CDMA/QPSK channels in parallel. In Synchronous CDMA (S-CDMA) mode or Quasi-Synchronous CDMA (QS-CDMA), the receiver is operating as a dual (Pilot and Traffic) demodulator. This option is e.g. used in high capacity CDMA-based VSAT star networks. The chips of the spreading sequence can be modulated in BPSK, QPSK, OQPSK (Offset QPSK), QPN (Quadri-Phase Pseudo Noise, i.e. using different spreading codes on I- and Q-branch) and OQPN (Offset QPN) and the differential PSK versions of these schemes. The amplitude levels of the I- and the Q-branch can be separately adjusted, allowing transmit power control capability over a 20 dB range. The transmitter and the receiver can be configured in all the above mentioned demodulation schemes and modes. Full flexibility is provided by 4 on-chip synthesizers: sampling and carrier frequency synthesizers, both for the transmitter and the receiver. The sampling synthesizers generate the adjustable oversampling clocks up till 20 MHz, while the carrier frequency synthesizers generate carrier waveforms at an intermediate frequency (IF), freely programmable up till 10 MHz. Additionally, the ASTRA offers a carrier phase step input, which allows a frequency jitter-free carrier reconstruction loop. The chip matched filters (CMF) in transmitter and receiver are SRRC (Square Rooted Raised Cosine) filters, implemented as 35-th order FIR filters. The roll-off factor of 0.4 is convenient for a wide range of applications. The transmitter CMF operation results in a transmit spectrum with sidelobes suppressed at least for 25 dB. The spreading and correlating pseudo-noise (PN) sequences are fully programmable. The maximum code length is 1,023, hence providing a Processing Gain of over 30 dB! Immediate swapping between different downloaded PN-codes is possible. In the receiver, 4 codes are stored during setup: an I- and a Q-code for the pilot channel, and an I- and a Q-code for the traffic channel. Normally, the received data are demodulated in the traffic channel. The pilot channel can be used for network synchronization purposes only, but it can as well be modulated with data, thus doubling the receiver’s demodulation capacity. The receiver computes 7 complex correlation values per symbol, used by the DSP to control all synchronization loops. The SC2001 ASTRA is processed in a 0.6 micron CMOS technology, and packaged in a 100-pin QFP for SMD mounting. FEATURES:
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DIRAC
Digital Spread Spectrum Receiver with ARM microprocessor Core
APPLICATIONS
The SC3001 DIRAC is a single-chip direct sequence spread spectrum receiver. Its key features are the integration of an ARM6 core on-chip, a flexible intermediate frequency (IF) downconverter, a Chip Matched Filter and 7 complex parallel correlators, making the chip suited for a wide application area. Because of the integrated 32-bit RISC ARM6 processor core, the SC3001 DIRAC IC implements a complete receiver, and requires no external processor. The DIRAC performs digital downconversion from a programmable Intermediate Frequency up till 10 MHz, Square-Rooted Raised Cosine (SRRC) filtering, fully programmable despreading, frame extraction and user interface tasks which are necessary to convert a sampled IF signal to data. The on-chip RS-232 UART module provides an integrated data and control I/O interface. The ARM6 core offers the benefits of a standard programmable component, such as a short design time and programmability, as well as the availability of development tools, like a C-compiler and a debugger. The customized hardware gives the chip the extra performance, which cannot be reached with standard components, at low cost and low power. The features of the resulting IC are ideal for mobile communication terminals. The ARM6 C-compiler allows to port common functions easily across applications and develop the low rate demodulation and control routines late in the design cycle of the final product. It hence allows to fine-tune the final program after field measurements. The SC3001 DIRAC can operate both in CDMA (Code Division Multiple Access) and non-CDMA mode. In default CDMA mode, transmitter and receiver are able to demodulate 4 channel CDMA/BPSK or 2 CDMA/QPSK channels in parallel. In Synchronous CDMA (S-CDMA) mode or Quasi-Synchronous CDMA (QS-CDMA), the receiver is operating as a dual (Pilot and Traffic) demodulator. This option is e.g. used in high capacity CDMA-based VSAT star networks. The chips of the spreading sequence can be modulated in BPSK, QPSK, OQPSK (Offset QPSK), QPN (Quadri-Phase Pseudo Noise, i.e. using different spreading codes on I- and Q-branch) and OQPN (Offset QPN) and the differential PSK versions of these schemes. The receiver can be configured in all the above mentioned demodulation schemes and modes. Full flexibility is provided by 2 on-chip synthesizers: sampling and carrier frequency synthesizers in the receiver. The programmable sampling synthesizer generates the adjustable oversampling clock up till 20 MHz, while the carrier frequency synthesizer generates carrier waveforms at an intermediate frequency (IF), freely programmable up till 10 MHz. Additionally, the SC3001 DIRAC offers a carrier phase step input, which allows a frequency jitter-free carrier reconstruction loop. The chip matched filter (CMF) in the receiver is a SRRC (Square Rooted Raised Cosine) filter, implemented as a 35-th order FIR filters. The roll-off factor of 0.4 is convenient for a wide range of applications. The spreading and correlating pseudo-noise (PN) sequences are fully programmable. The maximum code length is 1,023, hence providing a Processing Gain of over 30 dB! Immediate swapping between different downloaded PN-codes is possible. FEATURES:
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