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ASTRA
DEVELOPMENT BOARD
Main features:
It can be equipped with Sirius forward error correction (FEC) algorithms. It allows to extend the SC2002 ASTRA Development Board with a large number of digital and analog interfaces, and other peripherals, such as a DALLAS 2404 real-time clock The GEMINI Development Board features 2 FPGAs, each supported by SRAM, flash EPROM and periphery. Both FPGAs are mapped into the memory map of the DSP on the SC2002 ASTRA Development Board. The functions of the GEMINI Board are controlled via the ASTRA Board user interface. This interface communicates to the host PC via the ASTRA Board UART Main features
SC9002
ASAP CDMA Development Board
Fully Programmable, runtime switcheable PN codes and code lengths up to 1023 providing 30 dB processing gain. Based on the SC2001 ASTRA IC for spreading , TX band limiting filtering, upconversion, downconversion, RX baseband filtering and correlation. Flexibility is offered through the parameterization of the SC2001 ASTRA. It also contains a XC4036XL FPGA, loaded with the ASAP SC9001 CDMA Acquisition, tracking and demodulation algorithms. It also allows you to implement and test your own proprietary CDMA demodulation algorithms in real-time. All analog and digital interfacing to an RF frontend and a host processor is included on the board. Synchronous CDMA basestation development is fully supported. RRC pulse shaping with 25 dB out-band suppression. CDMA/FDMA channelization is supported. Analog interfacing is at a programmable intermediate frequency between 0-10 MHz Features:
DataSat CDMA Development System The DataSat CDMA Development System from Sirius Communications provides the physical layer equipment for satellite ground stations exploiting n * 64 kbit/s bidirectional data traffic. Spread spectrum/CDMA modulation provides efficient interference rejection, low power spectral density and inherent additional security. Applications include low cost VSAT data communications and transport of Internet data over existing geostationary transponders. The DataSat Development System is directly compatible with Sirius Communications' ASTRA Development Board and Development Accelerator for satellite terminal prototyping. More information can be found on the satellite communications page The DIRAC Development Board features the DIRAC CDMA/Spread Spectrum receiver chip (containing an ARM processor and a UART), RAM/ROM for the ARM, and an ADC. This allows full flexibility in demodulation schemes, data rates, despreading technique, tracking loops, synchronization algorithms, acquisition strategy, etc. The DIRAC Development Board provides a serial host interface, that you can connect to any RS-232 terminal or PC. This allows you to set parameters, check parameter settings, download software on the ARM processor, download codes into the despreader of the DIRAC chip, measure Bit Error Rates and other performance measures via a terminal or PC. More information can be found on the DIRAC page The SC2003 Extension Board is an auxiliary board that combines a number of functions. It allows to connect two or more SC2002 ASTRA Development Boards to:
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CDMA
DEVELOPMENT ACCELERATOR
The effect of typical parameters of the ASTRA Development Board can immediately be quantified using the CDMA Development Accelerator.
The SC13002 CDMA Development Accelerator is our NEW Windows-based CDMA Modem Development Kit and is available with a 32-bit parameter setup and command interface, and a graphical interface for realtime vizualization of receiver signals and constellation plots. Fast downloading of DSP execution code is also supported.
CDMA Modem Development Kit (See also the Windows-based CDMA Development Accelerator). The DOS-based CDMA Development Kit allows to continuously monitor in real-time up to 6 simultaneous receiver signals, such as correlation values, the receiver phase error, the AGC value, the carrier recovery and the timing recovery. A complex constellation diagram can also be shown. These measurements allow to quickly evaluate the performance of a receiver, and to tune the transmitter and/or receiver parameters. The ASTRA Development Board allows to program a huge range of modem parameters, and to derive Bit Error Rate (BER) figures. The effect of typical parameters of the Development Board can immediately be quantified using the ASTRA Development Kit. For instance, the step response of the PLL for carrier recovery can be visualised as a function of the PLL gain and PLL bandwidth. The ASTRA Development Kit consists of the following parts: 1. Development Kit Monitor software
At the right of the screen, the constellation plot of the demodulated QPN signal is shown. The Development Kit Monitor software can simultaneously handle 6 measurements out of a set of 32 receiver signals. This set can be freely assigned by the user, and the configuration can be done from the Development Board terminal window. Any of the 6 measurement channels can be plotted on a time axis, or in a complex plane, or both at the same time. The following 2 examples the system under test uses QPSK with different codes of length 15 on the I and the Q branches. This is also called QPN (Quadriphase Pseudo-Noise). At the left of the screen, the 2 upper function plots show snapshots of the correlation data of I and Q channels with each code, as a function of time. The third functional plot shows the chip frequency offset at the receiver (D_RX_FCHIP) and the frequency offset (D_RX_CARR) of the receiver carrier, as a function of time. Lock-in behavior of carrier tracking PLL As a result of a carrier frequency step at the transmitter side, the receiver carrier frequency starts to produce a beatnote, that slows down in frequency until lock is reached. During pull-in, correlation values are unusable, and become stable again when lock is reached. The receiver chip frequency offset (D_RX_CARR) remains unaffected. The transient behavior results in constellation dots outside the main spots.
Receiver response to step in transmit chip frequency. As a result of a chip frequency step at the transmitter side, the receiver chip frequency (D_RX_FCHIP) offset starts evolving towards a new stable value. The receiver carrier tracking loop (see D_RX_CARR) goes through a transient behavior, due to the coupling with the chip frequency tracking loop, and then reaches again its original value. 2. ASTRA software extension The ASTRA software running on the TMS LC31PQL is extended with a separate monitor process, that runs on the frequency of one of the internal timers of the TMS. This monitor process selects 6 out of 32 measurements and sends them to the PC via the ISA board.This set of 32 monitor signals is updated by the ASTRA receiver process every symbol. To match the slower speed of the PC, the selected measurements are automatically downsampled by the monitor process. However, independent of the speed of the PC running the Development Kit Software, the measurement set is always kept consistent. The faster the PC, the higher the resolution of the measurements plotted on the screen of the PC. The TMS monitor process is provided as source code, and is open to the developer, who can add his own signals to observe via the Development Kit, up to a maximum of 32 signals. 3. ISA interface board The ASTRA Development Board communicates to the PC via an ISA interface board. ASTRA
Compatible Baseband to 70 MHz IF converter
ASTRA compatible 2.4 GHz radio Front-end The S-Band radio consists of triple conversion up and down converters. Both converters operate from the same local oscillator. The unit is intended as an on-the-air evaluation add-on unit for the SIRIUS Communications ASTRA Development board. The radio is contained in a metal sheet housing to assure proper RF shielding and is equipped with SMA connectors (SMC connectors are available upon request) and feed-through capacitors for the power supply and control lines. The radio is built with standard, readily available MMIC components. As such, the unit is optimized for performance and flexibility rather than for low power consumption, cost and size. The receiver is equipped with a 2.2 dB noise figure LNA (output IP3 of 18.5 dBm). The part is set for best noise figure. If a higher IP3 is required -max 26.5 dBm- this can be set. In that case the NF will increase to 2.6 dB. The receiver has an 80 dB AGC amplifier that can either be controlled externally or internally through the RSSI signal. The transmitter delivers an output power of 10 mW and the unit can be easily modified to deliver more output power (max 40 mW). The output power level can be controlled from the ASTRA development board. HPA’s that deliver 10 Watt and more are available upon request. The oscillator is based upon a TCXO and multiplier chains. This guarantees stable and clean LO signals. The standard transmit and receive frequencies are set at 2.442 GHz. Baseband filtering is done with a standard low pass filter and can be set at cut-off frequencies of either 5 or 8 MHz depending on the IF frequency. Receiver and transmitter antenna connections can be either separate or routed through an on-board (solid state) antenna switch. The two antennas delivered with the radio are single patch microstrip antennas, linearly polarized with 5 dB of gain. Circularly polarized patches and high gain antennas are available upon request. The IF in and output connections match the specifications of the ASTRA Development Board. Besides IF
connections and power supply (5 Volt) the radio has the following control
signal connections: individual power control for LO, RX and TX, Transmit/Receive,
AGC in and RSSI out.
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