1.Can the ASTRA chip of Sirius Communications provide fast chip phase acquisition for long codes, still allowing low power consumption?

Yes, indeed. The solution consists of only 2 components: the ASTRA chip, which has a number of parallel sliding correlators on-chip, and an external device to perform fast acquisition (e.g. implemented on an FPGA). Once the acquisition phase has been completed (can be in a single symbol period) and the receiver is in lock, the flexibility of the ASTRA allows to switch to internal symbol clock generation, based on the sliding correlators operation. When in lock, the external device is disabled. As a result, fast acquisition can be obtained for long codes (e.g. PN code length 1,023), while low power consumption is assured by switching off the external circuits during the tracking phase.

2. What is the chip phase acquisition time when using the on-chip correlators?

For a resolution of 0.5 chips, the acquisition time is (2 * Code_length)/3 symbol periods. As explained in the answer to FAQ 1, immediate acquisition is possible when using an extra external device.

3. Are the chips suited for miniaturized satcom terminals?

The ASTRA and DIRAC chips integrate the full digital baseband functions for a satellite transceiver or receiver, respectively. A variety of PSK-based modulation schemes can be selected. Transmit and receive and-limiting filters (SRRC) are on-chip, as well as digital up- and downconverters to and from a low Intermediate Frequency. The on-chip receiver can be configured as a dual-mode receiver able to downconvert and demodulate Pilot and Traffic channels, as used in S-CDMA (Synchronous CDMA) networks. Furthermore a noise estimator function and a digital AGC loop are integrated. The chips provide also the conversion pulses for the A/D and D/A converters.

The chips are compatible with the INMARSAT-M and INMARSAT-B standards, and can be used as key components in terminals for CDMA-based constellations like Globalstar.

The ASTRA is a 3V device and comes in a 100-pin QFP for SMD mounting. The DIRAC comes in a 160-pin TE MQFP.

4. Does the ASTRA chip support the use of different codes for Acquisition and Tracking mode?

Yes. The on-chip RAMs can store 2 codes of maximum length 1,023 per branch (I and Q). This allows to swap synchronously from one code set to another when going from Acquisition mode to Tracking mode. This is very useful when one wants to use reserved codes with low cross-correlation properties during Acquisition to enhance the lock-in.

5. What's the purpose of the 32-bit ARM RISC core on the DIRAC spread spectrum receiver IC?

The purpose of the on-chip ARM core is 3-fold:

• Real-time control of the digital synchronization loops (AFC, DLL);
• Real-time Forward Error Coding/Decoding and Data Formatting/Deformatting;
• Off-line processing of raw data, e.g. for DGPS applications.

6. Can you cope with large Doppler shifts and Doppler rates?

Yes. Doppler shifts and Doppler rates depend very much on the application at hand. E.g.for LEO-based communications, the Doppler shifts can be in the order of several hundreds of kHz, while the Doppler rates can be as high as 200Hz/s. With the DIRAC chip, handling the Doppler effects is implemented in software on the on-chip ARM core, providing full flexibility according to the application.

7. Do the chips support multi-channel transmission and reception?

Yes, indeed! The ASTRA chip provides 2 QPSK/CDMA channels or 4 BPSK/CDMA channels in parallel, for transmission and reception. Moreover, N ASTRA chips can be combined in a Master/Slave configuration to allow N *2 or N *4 channels being processed in parallel. This can be e.g. applied for VSAT hubstations.

8. Do the chips support differential PSK schemes?

Yes. BPSK, QPSK, QPN, OQPSK and OQPN are selected via a programmable chip parameter, while the differential versions of these modulation schemes are realized by performing the differential encoding and decoding on the external processor (on-chip ARM core in case of the DIRAC chip).

9. How does the ASTRA chip compare to other available direct sequence spread spectrum chips?

The ASTRA has a number of unique functions and features on-board which are not present in other available direct sequence spread spectrum chips.

• PN codes and code lengths: The ASTRA allows fully programmable codes (download your favorite code in on-chip RAM at setup time) and code lengths up till 1,023.This provides a processing gain of over 30dB. Stanford Telecom's STEL-2000 (Z-2000) provides full flexibility, up till a length of 64. AMI's SX043 provides code lengths till 2,047, but is limited to Gold codes.

• On-chip transmit and receive band-limiting filters: The presence of these filters on the ASTRA allows to avoid costly SAW devices for bandpass filtering at IF, hence reducing the overall system cost considerably. This on-chip functionality is quite unique and is not found with other spread spectrum devices.

• On-chip up- and downconverters to and from a digital IF: allows the use of digital FDM combined with CDMA/QPSK, and has as important advantage that all synchronization loops are handled in the digital domain. The STEL-2000 has an on-chip digital downconverter; AMI's SX043 and the PRISM baseband processor from Harris require external circuitry for downconversion.

• Multiple channels for transmission and reception: the ASTRA is able to digitally combine 4 BPSK channels (or 2 QPSK channels), each with their own spreading code. This perfectly synchronous CDMA mode allows increasing the data rates while maintaining the spread bandwidth and code length, with minimal cross-correlation energy. This feature is not available with other chips currently available on the market.

The on-chip receiver chain can be configured as a dual demodulator, able to process the traffic signal (information signal) and a pilot signal simultaneously. The pilot signal carries the control data for S-CDMA networking.

A Phase Error Measurement block on the ASTRA allows the accurate measurement of chip phase differences between incoming signals and a reference signal. This function is used at the base station side of satellite networks operating in S-CDMA mode.

11. Can you deal with applications using variable data rates?

Yes. Data rates can be changed dynamically, and combined on-the-fly with changeable codes and code lengths. This is an important feature when different kinds of data require different processing gains. Data rates up till 5.875 Mbit/s can be realized.

12. Can Sirius Communications design a Direct Sequence Spread Spectrum ASIC according to specific customer's requirements?

Ofcourse! Sirius Communications offers its spread spectrum know-how and advanced ASIC design skills for the realization of next generation spread spectrum chips. Please refer to the Spread Spectrum Design Service information for more details.

13. Can you implement a digital FDM (Frequency Division Multiplexing) layer on top of a CDMA/QPSK scheme, using the ASTRA?

Yes! The on-chip digital up- and downconverters have a maximum IF at about 10 MHz. For example, if a single channel has a chip rate of 1 Mchips/s, then the bandwidth occupied is 1.4 MHz, due to the on-chip SRRC transmit filter. This means that 7 digital IF frequencies can be generated with the ASTRA. Because the ASTRA is also able to generate 4 BPSK/CDMA channels in one band, it is possible to generate 28 BPSK/CDMA/FDM channels or 14 QPSK/CDMA/FDM channels, for the example given.

14. Can you put the ASTRA and DIRAC chips in sleep mode for power savings?

Yes! The high-speed hardware can be switched off via software commands by the external processor (or on-chip ARM core, for the DIRAC). The current in the ASTRA chip draws drops then from 1.92mA/MHz in full operation mode to less than one tenth of this value in sleep mode. For the DIRAC chip, the current in operational mode is 1.17mA/MHz; switching the high-speed hardware off and leave the ARM core still operational takes 0.4mA/MHz.

15. What are the IS-95 features supported by the ASTRA Development Board?

The ASTRA Development Board provides an easy-to-use experimental platform for testing and setting up CDMA-based networks supporting features of the IS-95 standard:

• support of Synchronous CDMA by dual demodulator architecture: Pilot and Traffic channel modules are on the ASTRA chip.
• 64-chip Walsh sequences
• Multiple-correlator receiver for multipath recombination on-chip
• Vocoder functions, FEC and interleaving can be executed on on-board TMS320-LC31 (operating at 3.3V)
• CDMA base station aspects can be tested by slaving multiple boards.
• on-chip phase error measurement module (resolution 25 ns) for Synchronous CDMA operation of forward link
• forward and reverse link power control provisions
• Low implementation loss (Receive filter: 0.1dB, Direct Digital Synthesis block: typ. < 0.45dB) for high sensitivity

The versatility of the unique chip and board architecture allows to set up experiments to test CDMA-based third-generation mobile radio systems. The ASTRA Development Board is especially suited for handling runtime selectable variable data rates and PN code lengths.

16. Which modulation schemes can be supported by the ASTRA?

The following configurations are possible:

• Up to 4 parallel CDMA/BPSK channels:

This is achieved by using 4 different orthogonal codes for all I and Q branches. This mode is also called 2-channel QPN (Quadrature Pseudo Noise, i.e. 2 times double BPSK, with different codes on I and Q branches).

• Up to 2 parallel CDMA/QPSK channels:

This is achieved by using the same codes for I and Q channel of the same channel, but different codes on the different channels.

• Up to 4 parallel CDMA/DPSK channels:

The same as in the first case, but differential encoding/decoding is added on the external processor. Allows non-coherent tracking.

• Up to 2 parallel CDMA/DQPSK channels:

The same as in the second case, but differential encoding/decoding is added on the external processor. Allows non-coherent tracking.

• Up to 2 parallel CDMA/OQPN channels:

Offset QPN or Staggered QPN. On each channel, different codes are used for I and Q. The Q branch is delayed half a chip period w.r.t. the I branch. Allows the use of low-cost front-end amplifiers with limited linearity.

• Up to 2 parallel CDMA/OQPSK channels:

Offset QPSK or Staggered QPSK. The same codes are used on I and Q-branch. The Q branch is delayed half a chip period w.r.t. the I branch. Allows the use of low-cost front-end amplifiers with limited linearity.

If you want to use the chip in a pure PSK mode (i.e. equivalent to a code length of 1), then BPSK, QPSK, DPSK, DQPSK and OQPSK are possible.

All these modes are selectable via programmable registers.