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Standard
Cell Libraries
A standard cell library consisting of 500+ cells is available to support
digital logic with gate counts of up to 200K. Peregrine has internally
established a proven library development and qualification flow.
| Cell Library Summary |
| Voltage |
3.0V +/- 10% |
| Number of core cells |
450+ |
| Number of core functions |
100+ |
| I/O cells |
CMOS, Schmitt-triggered, Pull-up/Pull-down resistors |
| Gate density |
4.5K gates/mm2 |
| Clock frequency |
200+ MHz |
| Model deliverables |
Verilog |
| Synopsys .db |
| Cadence .alf |
| Synopsys .lib (optional) |
| Cadence .tlf (optional) |
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