The Renesas 32-/64-bit SuperHTM
embedded microcontroller and microprocessor family comprises a set
of upward compatible standard products as well as embedded cores for
a huge variety of applications. The SuperH™ family has been built
upon a set of upward compatible 32-/64-bit embedded cores.
SuperHTM Family's Main Features:
- Upward compatibility
- 32-/64-bit RISC architecture
- Basic 5-stage RISC instruction pipeline
- Low-power consumption
- Very high-code density through fixed 16-bit instruction length
- General purpose register bank (partly with additional banked
registers)
- Integrated MAC
- Target Applications:
- SH-1 for industrial control with integrated RAM and ROM.
- SH-2 for highly-integrated embedded control applications with
integrated caches and RAM, as well as mask ROM and embedded Flash.
Dedicated ASSP's have been developed for Powertrain applications.
- SH-2 DSP for embedded applications requiring additional DSP
performance offered by a combined RISC/DSP instruction set
architecture.
- SH-3 for high-performance, but cost-optimized embedded systems
featuring MMU, Caches, PCMCIA, SDRAM I/F, etc.
- SH-3 DSP for SH-3 applications requiring additional DSP
performance based on a combined RISC/DSP approach.
- SH-4 for high-performance applications requiring very high speed
featuring an integrated floating-point unit and graphics
accelerator.
- SH-5 for high-end 64-bit embedded multimedia system-on-chip
applications.
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