Information as of 2000-01-10
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P83Cx80; P87C380; Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.

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Features

• 80C51 type core
• On-chip oscillator with a maximum frequency of 16 MHz (maximum 0.75 µs instruction cycle)
• A DDC interface:
  - That fully supports DDC1 with specific hardware
  - That is DDC2B, DDC2B+, DDC2AB (ACCESS.bus) compliant, based on a dedicated hardware I²C-bus interface.
  - Contains a specific AUX-RAM buffer with programmable size (128 or 256 bytes) that can be used for DDC operation and shared as system RAM
• Automatic mode detection by hardware to capture the following information:
  - HSYNC frequency with 12-bit resolution
  - VSYNC frequency with 12-bit resolution
  - HSYNC and VSYNC polarity
  - HSYNC and VSYNC presence; needed for the VESA Device Power Management Signalling (DPMS) standard
• On-chip sync processor comprising:
  - Composite sync separation
  - Free running mode
  - Clamping
  - Pattern generation
• Two specific ports for the software I²C-bus interface
• 4 analog voltage outputs derived from an 8-bit Digital-to-Analog Converter (DAC)
• Ten 8-bit Pulse Width Modulation (PWM) outputs for digital control application
• One 14-bit PWM output for digital control application
• One 4-bit Analog-to-Digital Converter (ADC) with 2 input channels (for keyboard interface)
• LED driver port (Port 0); eight port lines with 10 mA drive capability
• One 8-bit port only for I/O function
• 20 derivative I/O ports with the specific port type configuration in each alternative function
• Watchdog Timer with a programmable interval
• On-chip Power-on-reset for low power detection
• Special Idle and Power-down modes for reduced power operation
• Optimized for Electromagnetic Compatibility (EMC)
• Operating temperature: -25 to +85 °C
• Single power supply: 4.4 to 5.5 V.

Differences from the 80C51 core

• No external memory connection; signals EA, ALE and PSEN are not present.
• Port 1, Port 2 and Port 3 (P3.0 to P3.3 only) mixed with other derivative functions.
• Timer 0/Counter 0 and Timer 1/Counter 1: external input is removed.
• External interrupt 0/INT0 replaced by Mode detection function.
• Standard serial interface (UART) and its control register are removed.
• Wake-up from Power-down mode is also possible by means of an interrupt.

Datasheet

Type nr.	Title	Publication release date	Datasheet status	Page count	File size (kB)	Datasheet
P83Cx80; P87C380	Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc.	12-Dec-97	Product Specification	84	420	Open

Blockdiagram

Products, packages, availability and ordering

Partnumber	Order code (12nc)	marking/packing	package	device status	buy online
P83C180AER/001	9352 423 10112	Standard marking * tube	SOT270	WIT	-
P83C180AER/001M1	9352 602 20112	Standard marking * tube	SOT270	WIT	-
P83C180AER/001S1	9352 435 30112	Standard marking * tube	SOT270	WIT	-
P83C180AER/001S2	9352 603 12112	Standard marking * tube	SOT270	WIT	-
P83C180AER/001T1	9352 508 90112	Standard marking * tube	SOT270	WIT	-
P83C180AER/002	9352 416 00112	Standard marking * tube	SOT270	WIT	-
P83C180AER/003	9352 416 10112	Standard marking * tube	SOT270	WIT	-
P83C180AER/01	9352 417 20112	Standard marking * tube	SOT270	WIT	-
P83C180AER/02	9352 417 30112	Standard marking * tube	SOT270	WIT	-

Please note, devices listed in the "Products, packages, availability and ordering" table marked with "WIT" are discontinued. Devices marked with "DOD" will be in the near future.
Contact your nearest sales or distributor office for the latest information on product status and availability.

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