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Information as of 2000-01-10
 Latest information online
P83C557E4, P80C557E4, P89C557E4; Single-chip 8-bit microcontroller
| Description |  |
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The P80C557E4/P83C557E4/P89C557E4 (hereafter generically
referred to as P8xC557E4) single-chip 8-bit microcontroller is
manufactured in an advanced CMOS process and is a derivative of
the 80C51 microcontroller family. The P8xC557E4 has the same
instruction set as the 80C51. Three versions of the derivative exist:
- P83C557E4 - 32 Kbytes mask programmable ROM
- P80C557E4 - ROMless version of the P83C557E4
- P89C557E4 - 32 Kbytes FEEPROM (Flash-EEPROM)
The P8xC557E4 contains a non-volatile 32 Kbytes mask
programmable ROM (P83C557E4) or electrically erasable
FEEPROM respectively (P89C557E4), a volatile 1024 × 8 read/write
data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I²C-bus), a "watchdog" timer, an on-chip
oscillator and timing circuits. For systems that require extra
capability the P8xC557E4 can be expanded using standard TTL
compatible memories and logic.
In addition, the P8xC557E4 has two software selectable modes of
power reduction - Idle Mode and power-down mode. The Idle
Mode freezes the CPU while allowing the RAM, timers, serial ports,
and interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic as well as bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system
clock, 58% of the instructions are executed in 0.75 µs and 40% in
1.5 µs. Multiply and divide instructions require 3 µs.
| Features | |
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- 80C51 central processing unit
- 32 K × 8 ROM respectively FEEPROM (Flash-EEPROM),
expandable externally to 64 Kbytes
- ROM/FEEPROM Code protection
- 1024 × 8 RAM, expandable externally to 64 Kbytes
- Two standard 16-bit timer/counters
- An additional 16-bit timer/counter coupled to four capture
registers and three compare registers
- A 10-bit ADC with eight multiplexed analog inputs and
programmable autoscan
- Two 8-bit resolution, pulse width modulation outputs
- Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
- I²C-bus serial I/O port with byte oriented master and slave
functions
- Full-duplex UART compatible with the standard 80C51
- On-chip watchdog timer
- 15 interrupt sources with 2 priority levels (2 to 6 external sources
possible)
- Extended temperature range (-40 to +85°C)
- 4.5 to 5.5 V supply voltage range
- Frequency range for 80C51-family standard oscillator:
3.5 MHz to 16 MHz
- PLL oscillator with 32 kHz reference and software-selectable
system clock frequency
- Seconds Timer
- Software enable/disable of ALE output pulse
- Electromagnetic compatibility improvements
- Wake-up from Power-down by external or seconds interrupt
| Datasheet | |
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