|
|
Information as of 2000-01-10
 Latest information online
PCK2509S; 50 - 150 MHz 1:9 SDRAM clock driver
| Description |  |
|
The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2509S operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the PCK2509S does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the PCK2509S requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The PCK2509S is characterized for operation from 0°C to +70°C.
| Features | |
- Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications
- Spread Spectrum clock compatible
- Operating frequency 50 to 150 MHz
- (tphase error - jitter) at 100 to133 MHz = ± 50 ps
- Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
- Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
- Pin-to-pin skew < 200 ps
- Available in plastic 24-Pin TSSOP
- Distributes one clock input to one bank of ten outputs
- External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input
- On-Chip series damping resistors
- No external RC network required
- Operates at 3.3 V
- Inputs compatible with 2.5 V and 3.3 V ranges
| Datasheet | |
| Find similar products: | |
PCK2509S links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category.
|
