Information as of 2000-01-10
 Latest information online 

PCK857; 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

• Description • Features • Datasheet • Find similar products

To be kept informed on PCK857, subscribe to eNews.

Description

Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable.

Features

• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications
• 1-to-10 differential clock distribution
• Very low skew (< 100ps) and jitter (< 100ps)
• 3V AV_CC and 2.5V V_ddq
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16857 and CBT3857

Datasheet

Type nr.	Title	Publication release date	Datasheet status	Page count	File size (kB)	Datasheet
PCK857	66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver	10-Dec-98	Preliminary Specification	8	62	Open

Find similar products:

 PCK857 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category.