Internally the SAA6750H uses a hardware solution for data compression and a specially developed high performance processor for control purposes. This programmable embedded Digital Signal Processor (DSP) approach allows Philips to tailor various customized sets of functions for this IC. Contact Philips for information on available software packages.

Function

The SAA6750H is a stand-alone single chip video encoder performing real time MPEG2 compression of digital video data.

The video data input of the SAA6750H accepts a digital YUV video data stream in ITU-T 601-format. PAL standard at 50 Hz and 720 pixel by 576 linesas well as NTSC at 60 Hz and 720 pixel by 480 linesare covered. The video synchronization may either follow ITU-T 656 recommendation or can also be supplied by external signals. The external reference clock VCLK = 27 MHz has to be synchronized to the video data. Philips Semiconductor’s SAA7111 product family provides a suitable video data stream and reference clock. Other sources are also supported by the flexible I²C-bus controlled data input interface of the SAA6750H. See Section 7.3 for detailed information.

An internal 4 :2 :2 to 4 :2 :0 colour format conversion is performed. Optionallya ITU-T 601 to SIF format conversion may be activated by I²C-bus control settings.

The real time data encoding part of the SAA6750H combines high-compression rates with high quality picture performance. This is achieved by the integration of Philips unique motion estimation algorithmproviding a search range of 128 by 128 pixelsand a patented motion-compensated noise filtering. The compression algorithm uses I or IP mode encoding. Normally it selects automatically the suitable mode but may also be forced only to I mode operation by I²C-bus control settings.

In contrast to the encoding part which is designed in dedicated hardwarecontrol functions and data stream handling tasks like e.g. header generation and bit-rate control are carried out by a dedicated control processor the so-called Application Specific Instruction-set Processor (ASIP). The ASIP’s microcode is contained in an internal RAM and is loaded via I²C-bus before start of operation. This architecture allows Philips to customize the SAA6750H to specific applications by generating different versions of the embedded microcode. Philips will provide software packages for several applications.

The ASIP is able to communicate with the outside world by I 2 C-bus and by a high speed parallel portthe GPIO port.

The SAA6750H generates an MPEG2 Elementary Stream (ES) in accordance with the MPEG2 standard ('ISO 13818-2'). Either Constant Bit-Rate (CBR) or Variable Bit-Rate (VBR) output data can be generated. The 16-bit data output interface supports Motorola (68xxx like) and Intel (xxx86 like) protocol style.

Data processing and control functions are managed by loosely coupled processes. FIFO memories are used to connect these processes. In addition to these internal storages the SAA6750H needs 4 ´ 4 Mbit of external DRAM memory (tRAC = 60 ns).

Selectable I²C-bus addresses and a special reset mode affecting the output pin behaviour allow the use of two SAA6750H devices in one application.

Features

• Digital YUV input according to 'ITU-T 601' and to 'ITU-T 656'
• NTSC and PAL (720 pixel x 480 lines at 60 Hz and 720 pixel x 576 lines at 50 Hz)
• Integrated colour conversion 4 :2 :2 to 4 :2 :0
• Integrated format conversion to SIF format (optional)
• Real time MPEG2 Simple Profile at Main Level (SP@ML) encoding
• IP frame or I frame only encoding supported
• Programmable Group Of Pictures (GOP) size
• Integrated motion estimationhalf pixel accuracy, search range 128 x 128 pixels
• Motion compensated noise reduction
• Elementary stream data output compliant to MPEG2 standard ('ISO 13818-2')
• Constant Bit-Rate (CBR) and Variable Bit-Rate (VBR) supported
• Bitstream output compatible to 16-bit parallel interface with Motorola (68xxx like) or Intel (xxx86 like) protocol style
• Adaptable to dedicated applications by embedded software
• Standard software package available (refer to software specification)
• No external host processor required
• High speed real time port for processor co-processor applications
• Only 4 x 4 Mbit external DRAM required
• I²PC-bus controlled
• Single external video clock 27 MHz
• Power supply 3.3 V
• Digital inputs 5 V tolerant
• Boundary Scan Test (BST) supported.

Applications

GENERAL

The SAA6750H can be applied within the following application domains:

• Video editing (PC applications)
• Camera signal transmission
• Digital Versatile Disc (DVD) authoring
• Video recording for surveillance
• Digital VCR.

All those systems have to compress video data in order to manage the storage or transmission of digitized video data. The SAA6750H can be handled for most of the applications as a stand-alone device. That means at start-up a microcode and a couple of I²C-bus settings are loaded and the SAA6750H is started. If neededsettings like GOP size or bit-rate are changed on-the-fly via I²C-bus.

Two basic modes of encoding will be supported by standard microcode packages: Encoding at VBR or CBR.

The GPIO port allows high speed data exchange between the embedded DSP and an external processor. Therefore applications like DVD-authoring are supported.

VIDEO EDITING (PC APPLICATIONS)

For video editing the SAA6750H can be interfaced gluelessly to a video input processor with ITU-T 565 compliant digital video output. In order to link the SA6750H to the PCthe use of the PCI bridge SAA7146 is recommend. By this bridge the MPEG2 video ES can be transmitted via the PCI-bus on a Hard Disc (HD). Furthermore all I²C-bus settings can be send from the PC via the bridge to the I²C components on the encoder board. The SAA7146 supports Pulse Code Modulation (PCM) audio capturing. Multiplexing with an audio stream or audio encoding can be done by the PC’s CPU.

CAMERA SIGNAL TRANSMISSION

In this application the SAA6750H will be located within a camera to compress the received digital video data for transmission. Typically VBR mode will be used.

DVD AUTHORING

For DVD authoring the video data has to be encoded in two steps. During the first step the complexity of the video sequence is measured and the results are stored externally. During the second pass the measured complexity is used as an input for the bit-rate control.

This application can be realized by a processor co-processor approach. The SAA6750Hwhich is working as a co-processorand a host processor are communicating via the GPIO port. A specific microcode package supports this mode.

VIDEO RECORDING FOR SURVEILLANCE

For surveillance systems VCRs with a huge amount of storage capacity are required. A high picture resolution is very important when there is action in the captured picture. The SAA6750H can control its encoded bit-rate by motion detection by its integrated motion estimation algorithm. Doing so the bit-rate can vary from 0.5 to 10 Mbit/s. VCRs with a storage space of 6 month are possible.

DIGITAL VCR

In stand-alone VCRs the SAA6750H works together with an audio encoder and a multiplexer. The SAA6750H is clocked by the video clock of the video input processor (SAA7111 or derivatives). A master clock is derived from the frame pulse. The video clock and master clock domain are de-coupled by a FIFO. The audio clock can be derived from the master clock. The video Packetized Elementary Stream (PES) packatizer has to take care of the fullness of SAA6750H’s output buffer.

Datasheet

Type nr.	Title	Publication release date	Datasheet status	Page count	File size (kB)	Datasheet
SAA6750H	Encoder for MPEG2 image recording (EMPIRE)	07-Sep-98	Preliminary Specification	64	311	Open

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