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Information as of 2000-01-10
 Latest information online
SAA7215; Integrated MPEG AVGD decoder
| Description |  |
This document is a reduced specification of the SAA7215.
The SAA7215 is a MPEG2 source decoder which
combines audio decoding and video decoding.
Additionally to these basic MPEG functions it also provides
means for enhanced graphics, background display and/or
on-screen display as well as encoding of output video.
Due to an optimized architecture for audio and video
decoding, maximum capacity in external memory and
processing power from the external CPU is available for
graphics support.
| Features | |
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General features
- Integrated MPEG AVGD decoder: Audio, Video and
Graphics decoding and Digital video encoding
- 16-Mbit or 32-Mbit external SDRAM for MPEG audio
and video decoding and graphics data storage
- Single or double external Synchronous DRAM
(SDRAM) organized as 1 M x 16 or 2 x 1 M x 16 (two
independant 16-bit data bus) interfacing at 81 MHz.
Due to efficient memory use in MPEG decoding, more
than 1 Mbit is available for graphics in the single
SDRAM configuration whereas 17 Mbits are available in
the double SDRAM configuration
- All basic operations of the AVGD decoder are possible
in both 16-Mbit and 32-Mbit configuration. Enhanced
performance is achieved by the use of 32-Mbit external
SDRAM.
- Targeted to BSkyB 3.0 and Canal+ basic box and web
box specifications
- Fast 16-bit data + 22-bit address synchronous or
asynchronous interface with external controller at up to
40.5 MHz
- Dedicated input for compressed audio and video in PES
or ES in byte wide or bit serial format. Accompanying
strobe signals distinguish between audio and video
data. Transport stream error connection available.
- Audio and/or video can also be input via the CPU
interface in PES/ES in 8 or 16-bit parallel format
- Single 27 MHz or 40.5 MHz external clock for time base
reference and internal processing. Internal system time
base at 90 kHz can be synchronized via CPU port. All
required decoding and presentation clocks are
generated internally.
- Flexible memory allocation under control of the external
CPU enables optimized partitioning of memory for
different tasks
- Optimum compatibility with T-MIPS controller SAA7214
- Boundary scan testing implemented
- External SDRAM self test
- Supply voltage: 3.3 V; package: SQFP208.
CPU related features
- 16-bit data, 22-bit address, Chip Select, Data Strobe
and DaTa ACKnowledge external control protocol
- Fast 16-bit data + 22-bit address synchronous interface
with the SAA7214, at up to 40.5 MHz
- Asynchronous interface possible with external
microcontroller
- Support of fast DMA transfer
- Flexible bidirectional interface to external SDRAM
- High speed/Low latency interface with second graphics
SDRAM
- Byte access to the full SDRAM in the upper 16-Mbit
address range
- Independent memory mapping of SDRAM and control
registers
- Two programmable independent interrupt lines
available
- Supports Motorola 68xxx interfaces as well as LSI
L64108 interface.
MPEG2 system features
- Parsing of MPEG-2 PES and MPEG-1 packet streams
- Double system time clock counters
- Stand-alone or supervised audio/video synchronization
- Support for seamless time base change (edition)
- Processing of errors flagged by channel decoding
section.
MPEG2 Video features
- Decoding of MPEG-2 video up to main level, main profile
- Output picture format: CCIR-601 4 :2 :2 interlaced
pictures. Picture format 720 x 576 at 50 Hz or 720 x 480
at 60 Hz
- Support of constant and variable bit rates up to
15 Mbits/s for the elementary stream
- Digital video input/output interface on 8-bit,
27 MHz (Cb YCr Y multiplexed bus), at a CCIR-656
format
- Analog video output interface on both the RGB and
Y/C/CVBS formats
- Horizontal and vertical pan and scan allows the
extraction of a window from the coded picture
- Flexible horizontal scaling from 0.5 up to 4 allows easy
aspect ratio conversion including support for 2.21 : 1
aspect ratio movies. In case of shrinking an anti-aliasing
pre-filter is applied.
- Vertical scaling with fixed factors 0.5, 0,75, 1 or 2.
Factor 0.5 realizes picture shrink. Factor 2 can be used
for up-conversion of pictures with 288 (240) lines or
less. Factor 0.75 is used for letterbox presentation.
- Horizontal and vertical scaling can be combined to scale
pictures to 1/4 of their original size, thus freeing up
screen space for graphic applications like Electronic
Program Guides
- Non full screen MPEG pictures can be displayed in a
box of which position and background colour are
adjustable by the external microcontroller. Structured
background is available as part of the graphic features.
- Nominal video input buffer size for MP at ML 2.7-Mbit
- Video output may be slaved to internally (master)
generated or externally (slave) supplied HV
synchronization signals or CCIR-656 contained
synchronization signals. The position of active video is
programmable. Display phase is not affected by MPEG
timebase changes.
- Decoding and presentation can be independently
handled under CPU control
- Various trick modes under control of external
microcontroller:
- Freeze field/frame on I- or P-frames; restart on
I-picture
- Freeze field on B-frames; restart at any moment
- Scanning and decoding of I- or I- and P-frames in a
IBP sequence
- Single step mode
- Repeat/skip field for time base correction
- Repeat/skip frame for display parity integrity.
MPEG2 Audio features
- Decoding of 2 channel, layer I and II MPEG audio.
Support for mono, stereo, intensity stereo and dual
channel mode.
- Constant and variable bit rates up to 448 kbits/s
- Supported audio sampling frequencies: 48, 44 .1, 32, 24,
22.05 and 16 kHz
- CRC error detection with automatic mute
- Selectable output channel in dual channel mode
- Storage of last 54 bytes in ancillary data field
- Dynamic range control at output
- Independent channel volume control and programmable
inter channel crosstalk through a baseband audio
processing unit
- Muting possibility via external controller. Automatic
muting in case of errors.
- Generation of ‘beeps’ with programmable tone height,
duration and amplitude
- Support for up to 8 channels linear PCM elementary
audio streams with 8, 16, 20 and 24 bits/sample and bit
rates up to 6.144 Mbits/s
- 96 kHz LPCM samples will be mapped to a 48 kHz
multi-channel format
- Volume control for linear PCM samples in three steps:
-6 dB, -12 dB and -18 dB
· Burst-formatting of AC-3 elementary streams
(IEC 1937) and MPEG-2 multi-channel streams in ES or
PES format for interconnection with an external
multi-channel decoder via the digital audio output or the
IEC 958 output
- Serial multi-channel digital audio output with 16, 18, 20
or 22 bits/sample, compatible either to I2PS or Japanese
formats. Output can be set to high impedance mode via
the external controller.
- Serial SPDIF (IEC 958) audio output. Output can be set
to high-impedance mode.
- Clock output 256 or 384fs for external DA converter or
clock input. Output can be set to high-impedance mode.
- Audio FIFO in external SDRAM. Programmable buffer
size, at least 64-kbit is available.
- Synchronization modes: PTS controlled, PTS free
running, software controlled, buffer controlled
· PTS register can be set via external controller.
Programmable processing delay compensation.
Graphics features
- Graphics are presented in boxes independent of video
format
- Boxes can be up to full screen allowing double buffer
display mechanism
- Two independent graphics planes are available for
background and/or graphics overlay
- Two independent data paths with RGB 4 :4 :4 and
YCb Cr 4 :2 :2 formats available with independent
mixing
- RGB path transparent to YCb Cr format
- Screen arrangement of boxes is determined by display
list mechanism which allows for multiple boxes,
background loading, fast switching, scrolling,
overlapping and fading of regions
- Real-time anti-flickering performed in hardware.
Programmable hardware available for off-line
anti-flickering
- Hard edged or soft edged wiping of regions available
- Support of 2, 4, 8, 16-bit/pixel in fixed bit maps format or
coded in accordance to the DVB variable/run length
standard for region based graphics
- Chrominance down-sampling filter switched per region
- Display colours are obtained via Colour Look Up Tables
(CLUTs) or directly from bitmap. CLUT output can be
YCb Cr T at 8-bit for each signal component thus enabling
16 M different colours and 6-bit for T which gives
64 mixing levels with video. CLUT output can also be
RGBT with same resolutions. Non linear processing
available by means of LUTs.
- Conversion matrices available to allow any format on
any different data path (RGB or YCb Cr )
- Map table mechanism to specify a sub set of entries if
the CLUT is larger than required by the coded bit
pattern. Supported map tables are 16 to 256, 4 to 256
and 4 to 16.
- Graphics boxes may overlap vertically even inside one
graphics layer thanks to the use of flexible chained
descriptors
- Internal support for fast 3-D block moves in external
SDRAM through Data Manipulation Unit
- Data Manipulation Unit allows format conversion and bit
manipulation from a chained list of instructions
- Graphics mechanism can be used for signal generation
in the vertical blanking interval. Useful for teletext, wide
screen signalling, closed caption, etc.
- Support for a single down loadable cursor of 1 k pixel
with programmable shape. Supported shapes are
8 x 128 pixels, 16 x 64 pixels, 32 x 32 pixels,
64 x 16 pixels and 128 x 8 pixels
- Cursor colours obtained via two 16 entry CLUTs with
YCb Cr T at 6, 4, 4 respectively 2 bits and RGBT at 4, 4,
4 respectively 4 bits (or 4, 5, 3 respectively 4 bits).
Mixing of cursor with video and graphics in 4 levels.
- Cursor can be moved freely across the screen without
overlapping restrictions.
Teletext
Supported either with TTX-REQ/TTX interface, of by
CPU loading of TTX data in SDRAM.
| Applications | |
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The SAA7215 integrated MPEG AVGD decoder is aimed
at being used in MPEG digital TV applications. This
decoder is primarily designed to be connected to a
SAA7214 transport stream
descrambler/demultiplexer/microcontroller by means of
glueless interfaces even though connections to other
market demultiplexers and/or microcontrollers are
possible.
The SAA7215 can be used in any system where high-end
graphics are needed (associated SDRAM can be
extended to 32-Mbit) as well as in low cost systems (all
functions can be enabled with only 16-Mbit of associated
SDRAM). Compatibility is also targeted with SAA7217 and
SAA7219.
| Datasheet | |
| Products, packages, availability and ordering | |
Please note, devices listed in the "Products, packages, availability and ordering" table marked with "WIT" are discontinued. Devices marked with "DOD" will be in the near future.
Contact your nearest sales or distributor office for the latest information on product status and availability.
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