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Information as of 2000-01-10
 Latest information online
TDA8043; Satellite Demodulator and Decoder (SDD)
| Description |  |
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This document specifies a DVB compliant demodulator
and forward error correction decoder IC for reception of
QPSK and BPSK modulated signals for satellite
applications.
The TDA8043 can handle variable symbol rates without
adapting the analog filters within the tuner. Typical
applications for this device are:
- Single Carrier Per Channel (SCPC): two or more
QPSK or BPSK modulated signals in a single satellite
channel (transponder)
- Multi-Carrier Per Channel (MCPC): one QPSK or
BPSK modulated signal in a single satellite channel
(transponder)
- Simul-cast: QPSK or BPSK modulated signal together
with a Frequency Modulated (FM) signal in a single
satellite channel.
The SDD requires the analog in-phase (I) and quadrature
(Q) components as an input and provides 8-bit wide
MPEG2 transport packet data at the output. The outputs of
the SDD can be directly connected to a descrambler
(SAA7206) or a demultiplexer (SAA7205).
For evaluation purposes, the output can also be used to
monitor internal data, for example I/Q after demodulation.
The SDD requires a single clock frequency which is
independent of the received symbol rate, providing the
clock frequency is slightly higher than twice the highest
symbol frequency.
All loops to recover the data from the received symbols are
internal. No external loop components are required. Loop
parameters for the clock, carrier recovery and AGC can be
controlled via the I2C-bus.
The Forward Error Correction (FEC) unit has a built-in
state machine to achieve lock without knowing the system
parameters (depuncturing rate, spectral inversion, etc.).
Once lock is achieved, all necessary parameters can be
read via the I2C-bus. By programming these parameters in
advance lock can be achieved more quickly.
The SDD can be controlled and monitored via the I2C-bus.
An I2C-bus default mode is specified which makes it
possible to use the device by software control. A 4-bit
bidirectional I/O expander and an interrupt line are
available. By sending an interrupt signal, the SDD can
inform the microcontroller of its internal status (lock).
| Features | |
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- One-chip Digital Video Broadcasting (DVB) compliant
demodulator and concatenated Viterbi/Reed-Solomon
decoder with de-interleaver and de-randomizer
- 3.3 V supply voltage (up to 5 V allowed)
- Internal clock divider
- On-chip crystal oscillator
- QPSK/BPSK demodulator:
- Interpolator to handle variable symbol rates without
an external anti-aliasing filter
- On-chip Automatic Gain Control (AGC) of the analog
input I and Q baseband signals or tuner AGC control
- Two on-chip matched Analog-to-Digital Converters
(ADCs; 7 bits)
- Square-Root Raised-Cosine Nyquist filter with
programmable roll-off factor
- High maximum symbol frequency: 32 Msymbols/s
- Can be used at low channel Es/No
(Symbol energy-to-noise ratio)
- Internal carrier recovery, clock recovery and AGC
loops with programmable loop filters
- Two carrier recovery loops enabling phase tracking of
the incoming symbols
- Different modulation schemes: Quadrature Phase
Shift Keying (QPSK) and Binary-Phase Shift Keying
(BPSK)
- Signal-to-noise ratio (S/N) estimation
- External indication of demodulator lock.
- Viterbi decoder:
- Rate 1/2 convolutional code based
- Constraint length K = 7 with G1 = 171oct and
G2 = 133oct
- Supported puncturing code rates: 1/2 , 2/3 , 3/4 , 4/5 , 5/6 ,
6/7 , 7/8 and 8/9
- 4 bits ‘soft decision’ inputs for both I and Q
- Truncation length: 144
- Automatic synchronization to correct puncturing rate
and spectral inversion
- Channel Bit Error Rate (BER) estimation from
10 -2 to 10 -8
- External indication of Viterbi synchronization lock
- Differential decoding supported.
- Reed-Solomon (RS) decoder:
- (204, 188 and T = 8) Reed Solomon code
- Automatic (I2C-bus configurable) synchronization of
bytes, transport packets and frames
- Internal convolutional de-interleaving (I = 12; using
internal memory)
- De-randomizer based on Pseudo Random Binary
Sequence (PRBS)
- External indication of RS decoder sync lock
- External indication of uncorrectable errors (transport
error indicator is set)
- Indication of the number of lost blocks
- Indication of the number of corrected blocks/bytes.
- I2C-bus interface:
- I2C-bus interface initializes and monitors the
demodulator and Forward Error Correction (FEC)
decoder with standby mode; when no I2C-bus is
used, default mode is defined
- 4-bit I/O expander for flexible access to and from the
I2C-bus
- I2C-bus configurable interrupt pin
- Standby mode for reduced power consumption.
- Package: QFP100
- Boundary scan test.
| Applications | |
- Demodulation and FEC for digital satellite TV.
| Datasheet | |
| Products, packages, availability and ordering | |
Please note, devices listed in the "Products, packages, availability and ordering" table marked with "WIT" are discontinued. Devices marked with "DOD" will be in the near future.
Contact your nearest sales or distributor office for the latest information on product status and availability.
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TDA8043 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category.
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