1999-06-01, BG9903,
Backgrounder From Philips Semiconductors

Once again, with the introduction of its new SiliconMAX™ family of power MOSFETs, Philips Semiconductors has achieved a quantum leap in device performance by adopting an innovative approach to device fabrication and package utilization. The result is large package MOSFET performance in small packages.

Modern power MOSFETs are all made up of a large number of small MOSFET 'cells' connected together in parallel on a single silicon die. As with all switching devices, one of the keys to minimizing power dissipation in these MOSFETs is to keep their on-resistance (R_DS(on)) as low as possible.

The conventional approach to reducing the on-resistance in conventional vertical DMOS MOSFETs is to make each cell smaller so that a greater number can be accommodated on a given area of silicon. This increases the number of cells that switch in parallel, and hence reduces R_DS(on)

However, as the cells get smaller and closer together they also start to interact with one another, creating a J-FET effect between adjacent cells that tends to restrict vertical current flow through the device and hence limits the achievable R_DS(on) reduction. Although cell-size reduction has gone a long way to reducing R_DS(on) values, and allowed manufacturers to use smaller die sizes for a given R_DS(on) value, the limited reduction in on-resistance achievable using this technique still means that the devices must be housed in relatively large packages to handle the associated power dissipation. For example, current industry-standard 100-volt DMOS devices housed in the large TO220 packages required to switch high load currents cannot achieve R_DS(on) values lower than 25 milliohms.

Conventional DMOS power MOSFETs also suffer from another disadvantage. Increasing die size to accommodate a larger number of MOSFET cells incurs the penalty of considerably increased drain-gate capacitance and resultant gate-charge (Q_GD), which adversely affects switching losses - the other major contribution to power dissipation in power MOSFETs. With conventional DMOS technology you can have low DC power losses (low R_DS(on) values) or low switching losses (low Q_GD values), but you cannot have both.

To create SiliconMAX™, Philips Semiconductors has exploited the inherent advantages of its TrenchMOS process to achieve dramatic improvements in both cell density and R_DS(on) values, while also maintaining the low Q_GD values required for high-speed switching performance. As a result, SiliconMAX™ MOSFETs have very low DC power losses combined with very low switching losses.

The secret of the TrenchMOS process, and hence of SiliconMAX™, lies in its vertical gate structure, which eliminates the J-FET effect between adjacent MOSFET cells and provides a more direct current path from source to drain (see figure 1). At the same time, the narrow profile presented by the vertical gate structure in the direction of the drain (see figure 2) minimizes gate-drain capacitance and hence maintains a SiliconMAX™ MOSFET's Q_GD value at a low level. As a result, maximum advantage can be taken from increasing the die size to reduce R_DS(on) without adversely affecting Q_GD. The extremely low DC and switching losses that result from this type of construction mean that in many applications a conventional through-hole mounted TO220 packaged DMOS FET can be replaced with a surface-mounting D-PAK SiliconMAX™ MOSFET, reducing the size, weight and assembly cost of equipment. Alternatively, two industry-standard parts can be replaced by a single SiliconMAX™ device - reducing component count and volume, and thereby increasing the power density (W/mm³) of power supplies.

Figure 1 - TrenchMOS cell structure used in SiliconMAX™ MOSFETs

Figure 2 - Capacitances within the TrenchMOS cell structure

At the higher operating frequencies favoured in modern switchmode power supply and DC/DC converter design, the superior switching performance of SiliconMAX™ MOSFETS is a real advantage. As can be seen from figure 3a and 3b below, a SiliconMAX™ MOSFET exhibits around half the switching losses of a conventional DMOS device with the same R_DS(on) value, and its turn-on fall-time is around four times faster.

Figure 3a - Switching losses in a DMOS and SiliconMAX™ MOSFET at turn-on.

Figure 3b - V_DS fall-time for typical DMOS and SiliconMAX™ MOSFETs at turn-on.

Figure 4 below illustrates the considerably lower Q_GD values of SiliconMAX™ MOSFETs compared to DMOS FETs.

Figure 4 - Q_GD versus R_DS(on) for typical DMOS and SiliconMAX™ MOSFETs.

In practice, the advantages of using SiliconMAX™ MOSFETs compared to DMOS devices are further enhanced when you consider the thermal performance of each type. With equivalent heatsinking, SiliconMAX™ parts run 20% to 30% cooler than DMOS parts - a factor that can be utilized to improve equipment reliability. Alternatively, SiliconMAX™ parts can often be used without heatsinks or be used to carry higher load currents.

The combined advantages of these important new power MOSFETs from Philips Semiconductors will bring about a new generation of switchmode power supplies and DC/DC converters that are smaller, lighter and more energy efficient than their predecessors. Designs that previously required bulky through-hole mounting power components with complex heatsinking can now be migrated to fully automated surface-mount construction.

However, the benefits of SiliconMAX™ MOSFETs extend further than the products in which they are used. Their smaller size means that less materials resource and energy is used in their construction, less packaging is required to protect them during shipment, and less energy is expended during transportation and handling. So both before and after they are built into products, SiliconMAX™ makes an important contribution to Philips' EcoVision of a less power-hungry world.