1999-08-30, BG9905,
Backgrounder From Philips Semiconductors

To accompany press release: ESC-9975

Convergence of skills within Philips Semiconductors makes Nexperia possible
The idea of modular hardware and software design has already been pioneered within the company with the Philips STB Concept and the Philips Global TV Concept.  Nexperia is the next step in the evolutionary process bringing together additional skills and expertise from all over the company to make Nexperia a reality.

• Philips Semiconductors' set top box (STB) chipset technology, which has already been designed into over a million set top boxes worldwide for digital terrestrial and satellite reception, has a strong roadmap based on MIPS® processor cores.
• Over one hundred million of its One Chip TV ICs have been sold around the world making it the dominant solution for TV design with two out of three new TVs being based on it.
• VLSI brings extensive ASIC design experience and libraries of hardware and software IP.
• An extensive range of MIPS-based™ processor cores has been developed in house to provide solutions from low cost to high performance.
• TriMedia™ VLIW processors have proven themselves to be easy to program and provide superior media handling capabilities, making them the solution of choice for digital TVs for the US market as well as high performance video conferencing and video editing systems.

New features through software and programmable processors
Nexperia supports two types of processor. MIPS-based RISC processor cores provide control and support for interactive services with the MIPS architecture supporting a wide range of applications and operating systems including Windows CE. The TriMedia VLIW (Very Long Instruction Word) processor cores have been specially designed by the company to handle high performance, real-time media and communications processing and are more efficient at this task than general purpose RISC processors. When used as a pair, they provide a more cost effective solution than using more powerful and expensive versions of a single RISC processor.

Under Nexperia, one or other or both types of processors can be used in a single IC. Applications like a digital set top box could be fulfilled with a MIPS-based IC similar to the company's current range of set top box solutions, which are now being made Nexperia-compliant.

For more advanced versions with a combination of demanding control and media processing requirements, a MIPS and a TriMedia core can be used together on the same chip. The TriMedia processor supports multiple, real-time media processing for transport stream de-multiplexing, audio and video decoding, and communications processing. The MIPS processor would handle the control functions along with a broad range of interactive services including Internet browsing, email, etc. An additional benefit of the co-processor approach is that it provides additional processing power to support new applications, enabling products to have a long life via field software upgrades.

Applications such as an ATSC digital television receiver, which have low control processing requirements but need high performance media processing, could use a TriMedia only solution. In addition to handling media processing such as video and audio decoding, the TriMedia processor can serve as the system controller and support a Java Virtual Machine for Java applications, as well as an Internet browser and back channel communications.

TriMedia core for high performance video processing and flexibility
Philips Semiconductors' TriMedia architecture has proved ideal for applications that demand high performance media processing. The TriMedia core can process up to five instructions with each clock cycle and with a clock speed of 180 MHz achieves an execution rate of up to 7 billion operations per second. Several major consumer electronics companies are designing digital television receivers based on TriMedia processor: Samsung, Philips, and another leading company are already shipping TriMedia-based digital television receivers. Nexperia benefits from the growing library of TriMedia software and from the TriMedia Software Development Environment that supports application development and optimisation entirely in high-level languages. The TriMedia roadmap extends from the current 32-bit version to 64-bit versions that will be available in 2000 to provide designers with tremendous headroom for increasing performance to match the increased systems demands as more functions and features are integrated into Nexperia products. "The TriMedia processor provides flexible, high performance media processing that makes Nexperia very powerful," said Günther Dengel, Managing Director of Philips Semiconductors' Consumer Systems division. "It would take an expensive, powerful RISC processor and multiple DSP to match the capabilities of just one TriMedia processor."

MIPS Cores for Scalability and Software Compatibility
Philips Semiconductors has developed two MIPS-based™ processor core families for use as control processor cores within its Nexperia System On Chip (SOC) ICs: the PR39XX and the PR19XX.

"We chose the MIPS® architecture to be our standard because it is open," explained Gunther Dengel. "This has enabled us to develop our own core designs and, as a result, we have created highly optimised solutions to deliver either outstanding performance in the case of the PR39XX or tiny size and power consumption in the case of the PR19XX. This range of cores ensures that whatever the demands of the application are, we have the ideal core to drive it in terms of size, power usage and performance backed up with more powerful cores to provide scalability.

The use of MIPS in Nexperia guarantees the support of multiple operating systems and the ready availability of application software and development tools. For example, MIPS processors have become the de facto standard for running Windows CE with the majority of design wins in this arena. The MIPS architecture provides a familiar environment and interface for programmers to create new software for plus there is a wealth of existing MIPS-based software and third party support tools.

Philips Semiconductors will be continuously evolving these MIPS CPU families, adding features and using the latest sub-micron process to bring leading edge performance SOC solutions for the high volume consumer market, as well as adding in the near future a new family of 64-bit CPUs.

Nexperia Hardware Architecture
Nexperia defines a standard Hardware Architecture, common to all Nexperia-based products, shown on Diagram 1. This standard architecture is fundamental to achieve Nexperia's short time-to-market. Nexperia's Hardware Architecture specifies a set of architecture standards covering bus architecture and topology, interrupt architecture, inter-processor communication, endianess, data formats, SOC testing, etc. One of the most important aspects of this architecture is the set of buses selected:

• DVP-Memory Bus: for programmable digital video systems, the memory bandwidth is one of the most important resources in the system. With that in mind, Nexperia's DVP-Memory bus has been specified as a high bandwidth, low latency path for the video, graphics, and program/data transfers between memory, processors and hardware components.
• PI-Bus: this bus is used by the CPUs to perform Memory Mapped I/O (MMIO) transactions to the devices, e.g. reading device status registers and writing device control registers. Also, not all devices need the level of Direct Memory Access (DMA) performance possible with the DVP-Memory bus, and can use the PI-Bus for low/medium bandwidth DMA.
• DVP-Level 2: this interface is defined between the IP core and the DVP-Memory Bus, allowing the IP. It abstracts the hardware components from the memory technology used. This is all the more relevant under the uncertain market conditions of today with PC133, DDR and RDRAM as possible options for dynamic memory.

All the devices are build independently of the CPU type, i.e. MIPS and TriMedia cores, allowing many different product configurations to be built using the same library of re-usable devices: MIPS and TriMedia cores, MIPS core only, and TriMedia core only.

Multi-Processor Environment
Nexperia enables applications to be allocated to the most appropriate processor with seamless integration along with functions that are handled on peripheral blocks. Both processor cores share common external memory, and either processor can control any device block through an industry standard peripheral interface bus. See Diagram 1. By separating control functions and time-critical media processing functions on different processor cores, Nexperia can provide excellent response time to interactive services without interfering with the video and audio tasks (which could result in frozen video, missed frames and dropped audio).

This multi-processor environment gives tremendous headroom for designers, as it is easy to add more processing power to the design by using more powerful versions of the processors or additional processors. In addition, the multi-processor design enables manufacturers to partition memory to protect core functions from problems caused by later field upgrades. Both the TriMedia and MIPS processors are programmed using high-level languages such as C/C++ making it easy to do the programming, recompile and port the applications - unlike traditional, dedicated DSPs that usually have to be specially written in machine code or assembler language.

Nexperia Hardware Components
With the Nexperia building block approach, ICs can be tailored to support a broad range of capabilities, beginning with audio and video decoding and system control. For more feature-rich appliances, additional peripheral devices and more powerful processor cores can support advanced functions such as games, an Internet browser, digital video recording, and even video telephony.

The company's Nexperia-compliant hardware modules include: Video Memory-Based Scaler, Image Composition Processor, MPEG2 VideoDecoder, MPEG2/AC-3 Audio decoder, MPEG2 de-multiplexor, Picture Improvement Accelerator, 2D Accelerator, 3D Accelerator, Audio In/Out, SPDIF, IEEE1394, USB, SmartCard Interface, PCI, Main Memory Interface (MMI), UART, and I2C.

Nexperia Software Architecture
Together with the Nexperia ICs, Philips Semiconductors is introducing a software architecture for these products that supports multiple Operating Systems and middleware software, and abstracts platform functionality via consistent APIs, making the decision on how a certain function is performed (hardware or software) transparent to the application software. See Diagram 2. The Nexperia software is composed of:

• Nexperia Streaming Software: a layer that encapsulates the implementation of streaming media components (hardware and software). Philips Semiconductors has a rich library of streaming software: MPEG1/2 Video decoder, MPEG1/2 Audio decoder, AC3, AAC, Speech Synthesis, Speech Recognition, Text to Speech, 50 to 100 Hz scan rate conversion, Scaling, IPQ, Picture-in-Picture (PIP), Blending, Histogram, ISDN Modem, V36 Modem, V90 Modem, DSM/CC, TCP/IP/PPP, Teletext, WSS, CC/V-chip, PDC, MPEG Streamer, Conditional Access, Data Casting, MJPEG Decoder, MJPEG Encoder, MPEG Audio Encoder, etc.
• Nexperia Platform Software: consisting of device drivers for on-chip and off-chip devices. The code base for this software is operating system independent and can be easily targeted for different operating systems. All device drivers for a particular system reference design are provided by Philips Semiconductors.

The software layer of Nexperia provides a consistent basis for the whole product range with its different product configurations.

Multiple Operating Systems
Software developers also benefit from the Nexperia architecture supporting multiple operating systems such as ISI's pSOS®, several operating systems for Java® support, and Windows® CE.

Product Roadmap
The first Nexperia products, the NX-2600 and NX-2700, are designed specifically to support digital television receivers and are sampling now, with volume shipments beginning in Q1 2000. For more details, please see release "Philips Semiconductors debuts Nexperia DVP product for digital TV" dated 30 August 1999.

The Nexperia product roadmap includes four additional Nexperia products in development for release over the next two years. See Diagram 3. The next IC is the Nexperia NX-8100 designed for advanced set top boxes and is a dual processor IC with both MIPS and TriMedia cores.

Nexperia products are supported by a rich set of software development tools, libraries of application software modules from Philips Semiconductors and third party vendors. A complete DTV Developers Kit including reference design and software for an ATSC television receiver is available for the NX-2600 and NX-2700 processors.

Nexperia and TriMedia are trademarks of Philips Electronics NV.
MIPS is a registered trademark and MIPS-based is a trademark of MIPS Technologies Inc. All other trademarks are recognised as belonging to the relevant companies.

Diagram 1. A typical Nexperia IC