1999-09-20, BG9907,
Backgrounder From Philips Semiconductors

Essentially an SSP is a generic architecture for a given application domain, consisting of hardware and software modules, which are designed to be re-useable and are fully interoperable and compatible. Benefits of the SSP approach include the use of tested modules and a dramatic reduction in design creation times. For further information on SSPs, please refer to BG-9906, entitled "Further information on Philips Semiconductors' Silicon System Platforms", which can be found at www.semiconductors.philips.com/news/backgrounders/bg9906.html.

The Nexperia CIP is being developed as an SSP for the growing convergence of digital multimedia applications in the car, encompassing GPS-based telematics and navigation, driver information and in-car entertainment systems. The Platform encompasses a range of applications from basic low-end processors up to fully featured systems with extensive media and information processing capabilities. Many components of Nexperia CIP are derived from the Nexperia Digital Video Platform (DVP), providing re-use of tested modules of hardware and software along with buses and architectural structures across SSPs.

"Philips Semiconductors is already the number one supplier of ICs for in-vehicle networking, access and immobilization systems", said Pascal Langlois, vice president global market automotive at Philips Semiconductors. "Added to this deep knowledge of the automotive industry is our company's vast portfolio of consumer products. These two valuable competencies place us in a unique position to lead the way in providing in-car telematics/entertainment solutions."

A key feature of the SSP approach is the use of programmable processors that enable many of the functions to be performed by software. As a result, modifications to the products can be made by manufacturers right up to the last stages of production and even once in the field. At the heart of the  Nexperia CIP lie three powerful processor cores, which have all been developed by Philips Semiconductors.
MIPS-based™ RISC processor cores provide control and support for interactive services with the MIPS® architecture supporting a wide range of applications and operating systems including Windows CE.
The  TriMedia™ VLIW (Very Long Instruction Word) processor cores have been specially designed by the company to handle high performance, real-time media and communications processing and are more efficient at this task than general-purpose RISC processors.
Highly-parallel  R.E.A.L. (Reconfigurable Embedded DSP Architecture Low-cost/Low-power) Digital Signal Processor (DSP) cores provide speech and audio processing.

Under Nexperia CIP, either MIPS or TriMedia or both cores can be used in a single IC, with or without a R.E.A.L. DSP core. The MIPS processor, supported by the appropriate hardware modules and software, handles the control functions along with a broad range of interactive services including Internet browsing, email, etc. When there is a requirement for multiple, real-time media processing for transport stream de-multiplexing, audio and video decoding, and communications processing, a TriMedia processor core is added, providing a more cost effective and higher performing solution. An additional benefit of the co-processor approach is that it provides additional processing power to support new applications, enabling products to have a long life via field software upgrades.

Philips Semiconductors' TriMedia architecture has proved ideal for applications that demand high performance media processing. The TriMedia core can process up to five instructions with each clock cycle and with a clock speed of 166 MHz achieves an execution rate of up to 6 billion operations per second. Several major consumer electronics companies are designing digital television receivers based on TriMedia processor: Samsung, Philips, and another leading company are already shipping TriMedia-based digital television receivers. Nexperia CIP benefits from the growing library of TriMedia software and from the TriMedia Software Development Environment that supports application development and optimization entirely in high-level languages. The TriMedia roadmap extends from the current 32-bit version to 64-bit versions that will provide designers with tremendous headroom for increasing performance to match the increased systems demands as more functions and features are integrated into Nexperia CIP products.

Philips Semiconductors has developed two MIPS-based™ processor core families for use as control processor cores within Nexperia CIP: the PR39XX and the PR19XX. The MIPS architecture was chosen to be the standard for control functionality because it is open. This has enabled the company to develop its own core designs that are highly optimized solutions to deliver either outstanding performance in the case of the PR39XX or tiny size and power consumption in the case of the PR19XX. This range of cores ensures that whatever the demands of the application are, Philips Semiconductors has the ideal core to drive it in terms of size, power usage and performance backed up with more powerful cores to provide scalability.

The use of MIPS cores in Nexperia CIP guarantees the support of multiple operating systems and the ready availability of application software and development tools. For example, MIPS processors have become the de facto standard for running Windows CE with the majority of design wins in this arena. The MIPS architecture provides a familiar environment and interface for programmers to create new software for plus there is a wealth of existing MIPS-based software and third party support tools.

Philips Semiconductors will be continuously evolving these MIPS CPU families, adding features and using the latest sub-micron process to bring leading edge performance SOC solutions for the high volume consumer market.

Philips Semiconductors' R.E.A.L. DSP (Reconfigurable Embedded DSP Architecture Low-cost/Low-power) DSP technology answers these demands, allowing designers to incorporate advanced digital signal processing functions into high-volume automotive products where cost and/or power consumption are critical design parameters. As a low-power DSP using highly parallel architectures to overcome power and execution time obstacles, it provides the required processing power while remaining a cost-effective solution.

R.E.A.L. DSP technology is primarily designed to produce DSP cores that become integral parts of complete 'system-on-silicon' solutions. The R.E.A.L. DSP development platforms therefore integrate seamlessly into Philips Semiconductors' standardized ASIC design flow, enabling an extensive range of memory types, microcontrollers, peripherals and I/O sub-systems to be added to the final IC. Already fully proven in a range of telecom (PCD6002 digital telephone answering machine IC; and GSM baseband ICs) and audio applications, the R.E.A.L. DSP design platform also meets the short time-to-market and IP (Intellectual Property) re-use requirements of fast-moving consumer markets.

Today's automotive applications are starting to need processing capabilities comparable to those of PCs. However, the high power dissipation of devices based on PC technologies makes them unsuitable for the extended temperature range from -40 to +85 degree. The cost nature of PC technologies is also a reason for switching to DSPs, especially with the highly price-competitive nature of the automotive market. Additionally, automotive applications tend to be 'real-time', placing a further burden on the processor core in terms of time available to execute DSP algorithms.

Nexperia CIP defines a standard Hardware Architecture, common to all Nexperia CIP-based products. This standard architecture is fundamental to achieve Nexperia CIP's short time-to-market. Nexperia CIP's Hardware Architecture specifies a set of architecture standards covering bus architecture and topology, interrupt architecture, inter-processor communication, endianess, data formats, SOC testing, etc. One of the most important aspects of this architecture is the set of buses selected:
Memory Bus: for programmable digital video systems, the memory bandwidth is one of the most important resources in the system. With that in mind, Nexperia's Memory bus has been specified as a high bandwidth, low latency path for the video, graphics, and program/data transfers between memory, processors and hardware components.
PI-Bus: this bus is used by the CPUs to perform Memory Mapped I/O (MMIO) transactions to the devices, e.g. reading device status registers and writing device control registers. Also, not all devices need the level of Direct Memory Access (DMA) performance possible with the Memory bus, and can use the PI-Bus for low/medium bandwidth DMA.
Level 2: this interface is defined between the IP core and the Memory Bus. It abstracts the hardware components from the memory technology used. This is all the more relevant under the uncertain market conditions of today with PC133, DDR and RDRAM as possible options for dynamic memory.

All the devices are build independently of the CPU type, i.e. MIPS and TriMedia cores, allowing many different product configurations to be built using the same library of re-usable devices: MIPS and TriMedia cores, MIPS core only, and TriMedia core only plus R.E.A.L. DSP core if required.

Nexperia CIP enables applications to be allocated to the most appropriate processor with seamless integration along with functions that are handled on peripheral blocks. Both processor cores share common external memory, and either processor can control any device block through an industry standard peripheral interface bus. By separating control functions and time-critical media processing functions on different processor cores, Nexperia CIP can provide excellent response time to interactive services without interfering with the video and audio tasks (which could result in frozen video, missed frames and dropped audio).

This multi-processor environment gives tremendous headroom for designers, as it is easy to add more processing power to the design by using more powerful versions of the processors or additional processors. In addition, the multi-processor design enables manufacturers to partition memory to protect core functions from problems caused by later field upgrades. Both the TriMedia and MIPS processors are programmed using high-level languages such as C/C++ making it easy to do the programming, recompile and port the applications - unlike traditional, dedicated DSPs that usually have to be specially written in machine code or assembler language.

With the Nexperia CIP building block approach, ICs can be tailored to support a broad range of capabilities, beginning with audio and video decoding and system control. For more feature-rich appliances, additional peripheral devices and more powerful processor cores can support advanced functions such as games, an Internet browser, digital video recording, and even video telephony.

The company's Nexperia CIP-compliant hardware will include modules such as: Video Memory-Based Scaler, Image Composition Processor, MPEG2 VideoDecoder, MPEG2/AC-3 Audio decoder, MPEG2 de-multiplexor, Picture Improvement Accelerator, 2D Accelerator, 3D Accelerator, Audio In/Out, SPDIF, IEEE1394, USB, SmartCard Interface, PCI, Main Memory Interface (MMI), UART,  I²C, GPS Baseband,  CAN controller and future Car bus interfaces.

Nexperia Software Architecture

Together with the Nexperia CIP ICs, Philips Semiconductors is introducing a software architecture for these products that supports multiple Operating Systems and middleware software, and abstracts platform functionality via consistent APIs, making the decision on how a certain function is performed (hardware or software) transparent to the application software. The Nexperia CIP software is composed of:
Nexperia Streaming Software: a layer that encapsulates the implementation of streaming media components (hardware and software). Philips Semiconductors has a rich library of streaming software: MPEG1/2 Video decoder, MPEG1/2 Audio decoder, AC3, AAC, Speech Synthesis, Speech Recognition, Text to Speech, 50 to 100 Hz scan rate conversion, Scaling, IPQ, Picture-in-Picture (PIP), Blending, Histogram, ISDN Modem, V36 Modem, V90 Modem, DSM/CC, TCP/IP/PPP, Teletext, WSS, CC/V-chip, PDC, MPEG Streamer, Conditional Access, Data Casting, MJPEG Decoder, MJPEG Encoder, MPEG Audio Encoder, etc.
Nexperia Platform Software: consisting of device drivers for on-chip and off-chip devices. The code base for this software is operating system independent and can be easily targeted for different operating systems. All device drivers for a particular system reference design are provided by Philips Semiconductors.

The software layer of Nexperia CIP provides a consistent basis for the whole product range with its different product configurations.

Software developers also benefit from the Nexperia CIP architecture supporting multiple operating systems such as ISI's pSOS®, several operating systems for Java® support, and Windows® CE.

In addition to the powerful hardware blocks, front-end receivers include GPS, speech recognition and car radio. Various bus systems can be supported such as CAN. Peripheral I/O blocks are already available to cover speech recognition, CD/DVD and audio/video functions and others will be added. Software includes device libraries, functional libraries (speech recognition, graphics etc) and support for an operating system.

Philips Semiconductors, already a major player in automotive electronics, is a world-leader in communications and audio/video systems, with proven capabilities in areas such as car radio, where its chipsets are setting industry standards. For telematics functions, advanced systems such as GPS with integrated dead-reckoning are already under development. Philips Semiconductors can also apply unrivalled experience and an impressively broad product and technology portfolio to in-car TV, video and sound systems. Complementing these competencies, Philips Semiconductors adds in-depth expertise in LCD displays, CD and DVD, complete man-machine interface solutions and advanced speech recognition systems based on extensive research and development over many years.

Philips Semiconductors, a division of Royal Philips Electronics, headquartered in Eindhoven, The Netherlands, is the eighth largest semiconductor supplier in the world. It is a committed supplier of dedicated automotive systems and components focusing on a number of core areas: in-vehicle networks (IVNs), access and immobilization, and car 'infotainment'. In many of these areas Philips Semiconductors is an acknowledged leader and is driving the development of a single integrated car telematics platform. These 'system' areas are backed by a world-class and extensive range of dedicated discrete semiconductors and sensors, and a wide portfolio of standard products. Philips Semiconductors' innovations in digital audio, video, and mobile technology also position the company as a leader in the consumer, multimedia and wireless communications markets. Sales offices are located in all major markets around the world and are supported by systems labs.

Nexperia and TriMedia are trademarks of Philips Electronics NV.
MIPS is a registered trademark and MIPS-based is a trademark of MIPS Technologies Inc.
All other trademarks are recognised as belonging to the relevant companies.