1999-11-30, BG9910,
Backgrounder From Philips Semiconductors

Although other companies are producing 0.18 micron CMOS, the advanced new 0.18 micron process now up and running in Philips Semiconductors' MOS4 fab is optimised to produce the high-speed, high-performance chips required in leading edge consumer product applications.

Increasing the speed and performance of CMOS ICs requires more than just a geometry reduction. It also requires reductions in parasitic capacitances, together with highly efficient interconnect schemes and advanced new logic cell designs. Philips Semiconductors, the largest European semiconductor manufacturer, has therefore enhanced the 0.18 micron CMOS process (CMOS18) running in the company's MOS4 fab extension to use low-K dielectrics, an additional local interconnect metal layer and new high-density memory cells. By improving performance and reducing die area without unduly increasing the number of processing steps, these enhancements enable Philips Semiconductors to give its customers significant performance advantages while at the same time delivering the high-volume low-cost chip manufacturing for which it is well known. CMOS18 is also a dual-Vt (dual threshold voltage) process, allowing it to be tailored for high speed as well as low leakage applications, while its dual gate oxide also makes it compatible with higher voltage ICs.

Low-K dielectric reduces propagation delays

The different metal layers that interconnect the logic gates on a silicon chip are insulated from one another, and from the active silicon beneath, by ultra-thin layers of dielectric (non-conducting) material. However, the resultant metal-dielectric-metal and metal-dielectric-semiconductor structures that are formed create small capacitors (parasitic capacitance) that must be charged and discharged every time a logic signal propagates from one part of the chip to another. This results in the signal suffering a propagation delay that slows down its progress from one part of the chip to another and hence affects the chip's performance.

To overcome this problem, Philips Semiconductors' new CMOS18 process utilises Hydrogen Silsesquioxane based flowable oxide (HSQ) as the insulating layer - a 'low-K' (low dielectric constant) material that significantly reduces parasitic capacitance and hence shortens the propagation delays.

"Together with the lower sheet-resistivity of our metal layers, the effect of using this low-K dielectric material is to increase the speed of logic signals passing from one part of the chip to another by as much as 30% compared to other 0.18 micron CMOS processes," said Theo Claasen, Chief Technoloy Officer at Philips Semiconductors. "By greatly improving timing margins within the chip, this considerably simplifies IC design and allows the chips to be stretched to their maximum performance limits," he added.

Local Interconnect adds versatility, increases yield

Although short interconnect pathways, such as those between the individual gates in a logic cell or between adjacent cells, are less affected by propagation delay than long pathways, the routing flexibility of short interconnects is critical to achieving maximum gate density on a chip. Philips Semiconductors has therefore introduced an additional Local Interconnect Layer (LIL) to the 6 metal layers of the standard 0.18 micron CMOS process. Positioned below the normal metal layers at gate level and fabricated using tungsten metal instead of aluminium to achieve conductor widths as fine as 0.24 microns, the additional routing flexibility achieved by the LIL contributes to between 10% and 20% silicon area improvement for typical core cells.

"Even though the LIL adds a few extra steps to the process, which many would regard as decreasing the achievable yield, the introduction of this extra layer actually increases the overall yield that we can achieve in our CMOS18 process," said Claasen. "This is because the extra routing flexibility provided by the LIL means that the track spacing in the layer-1 metal can be made considerably wider, greatly reducing the sensitivity of layer-1 to defects."

New cells for greater chip density and non-volatile memory

In addition to migrating its existing CMOS cell libraries to 0.18 micron, Philips Semiconductors has introduced a number of new cells designed specifically for this process. For example, the increasing need for larger and larger SRAM blocks in the latest system-on-chip solutions means that SRAM blocks are becoming area critical in many designs. As a result, Philips Semiconductors has developed a special high-density SRAM cell for CMOS18, and will soon match it with a similar high-density dual-port SRAM cell.

Philips Semiconductor's advanced new CMOS18 process will also include a CMOS18 Flash option - extending the company's non-volatile memory roadmap and meeting specific requirements in telecom and smart card applications. This new Flash memory cell, which is based on a stacked-gate concept, is highly competitive and significantly smaller than 0.8 micron² in area.

Work is also underway to migrate the cell libraries of recently acquired VLSI Technology to the CMOS18 process, giving customers the benefits of a very broad ASIC design library, advanced ASIC design tools and short development cycles, together with Philips Semiconductors' world-class manufacturing facilities.