1999-02-11, ESC-9884,
Technical Backgrounder From Philips Semiconductors

In developing higher speeds and mixed-voltage capability for the I²C-bus, Philips Semiconductors was careful to retain the essential elegance, simplicity and low cost that made the original I²C-bus so popular, as well as ensuring it was fully compatible with existing systems by ensuring logic levels and bus protocols fully meet the current specification. Standard-mode (S-mode) - the original 100 kbits/s specification - is still widely used, while Fast-mode (F-mode) was introduced in 1992 to provide 400 kbits/s transfer. Address space has also been increased from 7-bit to 10-bit, allowing for up to 1024 additional slave addresses in line with the increasing popularity of the I²C-bus.

Implementing bi-directional mixed speed communication between Hs-mode and F/S-mode devices within a single I²C-bus system is simple. It requires just a single Hs-mode master device (which has two high-speed pins for communicating with other Hs-mode devices and two separate low-speed pins for communication with F/S-mode devices) and a specially-designed, low-cost bridge between the two different-speed sections. In mixed mode systems only one Hs-mode bridge is needed and this can be combined with an Hs-mode master.

As a multi-master bus, there can be more than one master Hs-mode device. To announce an Hs-mode transfer and for arbitration purposes, master devices use 8-bit master codes. These are reserved codes, which cannot be used for slave addressing, with the 3 least significant bits identifying each master. Thus there can be up to 8 Hs-mode masters in a single system. Preceding an Hs-mode transfer, arbitration and synchronization between competing masters is handled at F/S-mode speeds.

The bridge circuit recognizes a master code and separates Hs-mode and F/S-mode sections. This allows High-speed transfer at up to 3.4 Mbits/s between Hs-mode devices, but blocks Hs-mode transfers to the lower speed section. This has the additional advantage of lowering bus load and improving EMC behaviour without confusing F/S-mode devices. The bridge is transparent to arbitration and synchronization between the two speed sections and transfer between all connected devices is still possible at F/S-mode speeds because no master code is transmitted, so the bridge maintains the connection between the Hs-mode section and the F/S-mode section. Without the bridge, Hs-mode devices all simply function in 'Hs-mode only', or as F/S-mode devices in lower speed I²C-bus systems, ensuring the required downwards compatibility. Finally, the bridge may also perform a bi-directional level shift function between the two speed sections to mix, for example, 3 V Hs-mode and 5 V F/S-mode devices.

The same serial bus protocol and data format are used for Hs-mode as with the F/S-mode devices, except that arbitration and clock synchronization are not performed during an Hs-mode transfer to speed up bit handling. Because it is a true multi-master bus with arbitration, clock synchronization, stretching and acknowledge, Hs-mode requires no additional wires or pins for slave devices.

As an Hs-mode master device has two additional pins, if they are not needed (because it only has to communicate with other Hs-mode devices or because it is being used only at F/S-mode speeds with no system bridge), these pins can be used for other I/O functions, making I²C-bus an extremely flexible solution.