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1998-01-08 , E/IC-860/650
Technical Backgrounder From Philips Semiconductors

Philips Semiconductors continues its leadership in TV systems with the demonstration of a complete VSB (Vestigial Side Band) tuner front end and channel decoder chipset for Digital TV at the Consumer Electronics Show, Las Vegas


Philips Semiconductors has demonstrated a total system solution for handling Vestigial Side Band (VSB) signals for Digital TV. This demonstration board takes terrestrial signals and processes them to the stage of a digital MPEG transport stream, which is then handled by one of the company's TriMedia processors for use in a personal computer, TV or Set Top Box.

The two key front end chips are the VSB IF downconverter, which is either a TDA9829T or a TDA9819, and the Download PDF TDA8960, which the company believes to be the first integrated single chip solution for VSB integrated demodulation and decoding.

diagram1

Diagram 1: Tuner front end and channel decoder for VSB Digital TV

TDA9819 and TDA9829T downconverters
These downconverters work on IF frequencies from 38.9 MHz to 45.75 MHz, to handle the terrestrial applications of the standard 6 MHz VHF/UHF terrestrial TV channels (TV channels 2 to 69 in the US) and similarly, for cable applications, the standard 6 MHz VHF/UHF cable TV channels. They provide true synchronous demodulation with active carrier regeneration, very linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response.

They are both based on a design consisting of three AC-coupled, differentiator amplifier stages, with each differential stage comprising a feedback network controlled by emitter degeneration to control the IF gain. The TDA9819 provides the additional feature of being able to accept both digital video and analog TV input.

The gain controlled DVB-IF signal is down-converted to the symbol frequency by use of a four quadrant multiplier. The conversion signal is provided by the Voltage Controlled Oscillator (VCO) and Travelling Wave Divider (TWD). The Automatic Gain Control (AGC) detector charges/discharges the AGC capacitor to the required voltage for the setting of the IF and tuner gain in order to keep the DVB signal at a constant level. The output amplifier for the DVB signal has high bandwidth and delivers a 2V (p-p) signal.

The TDA9819 is available now in a 32 pin SDIP package and is priced in the region of $2.82 in quantities of 10,000, while the TDA9829T will be available in the next few months in a 20 pin SO package, priced in the region of $2.05 in similar volumes.

TDA8960
The TDA8960 is an 8-VSB demodulator and decoder for terrestrial applications that handles the channel decoding prior to the signals going to the source decoder for MPEG decoding. It functions as a one chip Advanced Television Systems Committee (ATSC)-compliant demodulator and concatenated trellis (Viterbi)/Reed-Solomon decoder with de-interleaver and descrambler. It is one of the first such devices to have a Forward Error Corrector (FEC) integrated onto the IC and to generate the Nyquist slope digitally rather than via the Surface Acoustic Wave (SAW) filter.

diagram2

Diagram 2: Simplified block diagram of the TDA8960

The IC requires a single "low IF" passband signal centred at half the 8-VSB symbol rate of 5.38 MHz as an input and provides 8-bit wide MPEG-2 transport packet data at the output. It requires a single clock frequency which is equal to twice the 8-VSB symbol rate. Most of the loop components needed to recover the data from the received symbols are internal. The only external loop components are a low cost DAC (Digital to Analog Converter) and VCXO (Voltage Controlled Crystal Oscillator) to generate the nominal 21.52 MHz clock for the ADC and IC, and an op amp integrator for the AGC (Automatic Gain Control). The loop parameters of the clock and carrier recovery can be controlled by the I2C bus.

The carrier recovery is performed completely internally and consists of a digital frequency and phase-locked loop (PLL). Datashaping is performed with a square root raised cosine (half Nyquist) filter with a roll-off factor of 11.5%. After symbol timing recovery, adaptive equalisation is performed based on the use of the ATSC field sync (trained equalisation ) and/or the 8-VSB data itself (blind equalisation), using a Decision Feedback Equaliser (DFE) structure.

After trellis decoding, the stream is de-interleaved with a convolutional de-interleaver (interleaving depth 52). The memory for de-interleaving is on-chip. The Reed-Solomon decoder is ATSC-compliant, has a length of 207 and can correct up to 10 bytes. Next, the decoded stream is de-scrambled using a PRBS (Pseudo Random Binary Sequence). Finally, the de-scrambler output is passed to a FIFO (First In, First Out) that prevents the appearance of irregular gaps in the output data.

The output of the VSB IC is an 8-bit wide MPEG-2 stream together with a clock that is fed into the MPEG-2 transport de-multiplexer, which can be a TriMedia processor. Some signal flags are provided to indicate the sync bytes and the valid data bytes. Uncorrected blocks are also indicated.

The TDA8960 will be available in a 64 pin QFP early this year and is priced in the region of $18 in 100,000 quantities.

Philips Semiconductors, a division of Philips Electronics NV, headquartered in Eindhoven, The Netherlands, is the ninth largest semiconductor supplier in the world and the fourth largest supplier of discretes in the world. Philips Semiconductors' innovations in digital audio, video, and mobile technology position the company as a leader in the consumer, multimedia and wireless communications markets. Sales offices are located in all major markets around the world and are supported by systems labs.

(Internet access required) TriMedia is a Trademark of Philips Electronics North America. All other trademarks are property of their respective owners.

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