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1998-12-02, BG9809,
Technical Backgrounder from Philips Semiconductors

Philips Semiconductors' BCD technology on Silicon On Insulator process offers greater power handling, improved robustness and easier design

Philips Semiconductors, the largest European semiconductor company, announces details of its first Silicon On Insulator (SOI) Smart Power process technology called A-BCD1 (Advanced Bipolar-CMOS-DMOS) - a single poly, double metal technology targeted for 12V to 60V applications. At the end of 1998, Philips Semiconductors will be the first company to start volume production of thin-film SOI Smart Power technology for consumer applications. This pioneering work has been carried out in close co-operation with the French company, SOITEC, the leading supplier of bonded 'SmartCut®' SOI wafers. The technology uses a 1.5 micron active silicon layer on top of a one micron layer of Buried OXide (BOX), see fig. 1.

SEM cross section of an A-BCD SOI wafer
Figure 1: SEM cross section of an A-BCD SOI wafer

The oxide layer allows for complete isolation of all the components formed on the chip and offers four key advantages as a result. First, the resistance when its transistors are in the on-state (Rds(on)) is reduced by more than 20% compared to equivalent bulk silicon processes, so that ICs made using A-BCD1 can handle much higher power levels as much less waste heat is produced.

Second, the absence of junctions between N- and P-type devices and the substrate makes the process intrinsically free from latchup (a situation that can occur in bulk silicon where transistors are overloaded and effectively become 'stuck' in the on-position). This means it virtually eliminates all the problems associated with cross-talk via the substrate, load dump and other accidental high external voltages. This greatly improves the robustness and reliability of A-BCD1 ICs and allows easy integration of multiple power devices, bridge rectifiers and flyback diodes on the same piece of silicon. This, together with the ability to construct ICs using CMOS, Bipolar, JFET and DMOS devices, enables real Smart Power circuits to be created.

Third, much greater packing densities - in the order of 20 to 30% smaller - can be achieved than on bulk silicon, especially for high voltages.

Fourth, parasitic capacitances are also significantly reduced and, together with the previous features, this makes it much easier and quicker to design in A-BCD1 SOI technology compared with standard bulk silicon processes. The elimination of parasites is especially important here because it is difficult to model these problem effects so that time-consuming experimental iteration processes have to be used to work out how to eliminate them from conventional designs.

Because of the above features, a key application of the A-BCD1 process is audio power amplifiers for car radios where voltage spikes from the starter motor or dynamo can be as high as 50V. This is no problem because A-BCD1 ICs can be made to tolerate up to 60V, plus the SOI-technology allows easy reverse-polarity protection. Also 'loss-of-ground' tolerance can be achieved without additional external components. Another application is automotive ICs with car area network (CAN) transceiver ICs first exploiting the A-BCD1 possibilities. Finally, the A-BCD1 process is ideally suited for creating ICs for use in motor drives, such as CD drives, printers and hard disk drives, where a collapsing hysteresis field in the coils can create voltage spikes.

The power handling of the DMOS power transistors made in A-BCD1 is much better than in bulk silicon because the Rds(on) is much lower so less waste heat is generated. The key part of the transistor where the resistance is critical is the drift region, which enables it to cope with the high voltages. In SOI this can be doped more, increasing the conductivity while keeping the breakdown voltage sufficiently high, because the BOX layer provides a counter-acting depletion layer to reduce the lateral field in the drift region (called the Reduced Surface Field or ReSurf Effect, a Philips discovery). The result of this lower Rds(on) is that designers have a choice of lower heat dissipation for the same size chip, a higher current handling capability from the same sized chip or a smaller chip with the same dissipation.

Three types of DMOS devices can be created using the A-BCD1 process, so that the die size (and therefore cost) can be optimised to provide the lowest Rds(on) for a given operational voltage. The LV-DMOS (Low Voltage DMOS) operates in the 18V region with an Rds(on) of around 50mOhm.mm2, MV-DMOS (Medium Voltage DMOS) operates in the 25V region with an Rds(on) of around 60mOhm.mm2, and HV-DMOS (High Voltage DMOS) operates in the 60V region with an Rds(on) of around 150 mOhm.mm2, see fig. 2. Complementary PMOS devices up to 60V are also available. Work on a next generation process, A-BCD2, with improved packing densities and offering 10-30% lower Rds(on) values, see fig. 2, is well under way and will enter volume production in 1999.

Trade-off between breakdown voltage and on-resistance of the N-type power DMOS transistors
Figure 2 : Trade-off between breakdown voltage and on-resistance of the N-type power DMOS transistors

The process uses a thick, 2.5 micron, second metal layer to limit the contribution of the metallisation system to the total on-resistance of the power transistors and to eliminate electromigration phenomena. The process can be optimised for lower voltages than 60V by just adjusting the drift region dope concentration of the DMOS devices, making it attractive for all power applications between 12 and 60V. Furthermore, a large set of MOS, DMOS (P- and N-type), bipolar, JFET and passive devices is available to facilitate the creation of optimised IC designs. Finally the process allows easy integration, i.e. with no additional masks, of a limited amount of OTP (One-Time-Programmable) memory that can be used for trimming, non-linearity correction or device 'signature'.

ICs made in A-BCD1 also have the advantage of a greater heat tolerance, being able to function up to 160°C compared with bulk silicon's 125°C. This is because leakage currents, which occur in the reverse biased junctions used to isolate components in bulk silicon and increase exponentially with temperature, are absent because the isolation in A-BCD1 is done by the BOX layer. This, in combination with the lower Rds(on), means that high power handling ICs can be created without the need for heat sinks, reducing both size and costs.

The cost of the SOI starting material is currently still high but this is compensated for by the low number of masking steps in Philips Semiconductors' A-BCD1 process, i.e. 13 being 3-4 times lower than an equivalent bulk silicon process. In addition, its improved packing density, greater power handling and simplified designs enable products made using it to be commercially priced. The first A-BCD1 products will be a family of Class-D amplifiers that will be available shortly. Other products will include Class-A/B amplifiers, CD-motor drivers and car area network (CAN) transceiver ICs.

Philips Semiconductors, a division of Royal Philips Electronics, headquartered in Eindhoven, The Netherlands, is the ninth largest semiconductor supplier in the world. Philips Semiconductors' innovations in digital audio, video, and mobile technology position the company as a leader in the consumer, multimedia and wireless communications markets. Sales offices are located in all major markets around the world, and are supported by regional customer application labs.

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